Modern day semiconductor memories have been produced with very high storage capacities (hundreds of millions of bits) with scaling down of transistors and the power source voltage. However, an incremental increase in storage capacity with low power source voltage tends to reduce the reliability of these memory devices. For example, the scaling down of transistor has reduced the capacitance in each memory cell, often resulting in random one-bit error due to cosmic radiation or alpha radiation. These random one-bit errors occur frequently enough that such errors can no longer be ignored. The increase in the number of cells in memory devices tends to reduce the mean time to failure (MTTF) of the entire memory device. As a result, the level of reliability required for the memory device become increasingly stringent. In some applications, semiconductor memory devices have been implemented with error correction to improve the reliability of the memory devices.
Errors in semiconductor memory devices are normally classified as “soft” errors and “hard” errors. Soft errors are random, non-repetitive and non-permanent change in the state of a memory cell. Soft errors are caused by occasional electrical noise or are induced by radiation, such as cosmic rays, that affects a very limited number of memory cells at a time, and these soft errors may be recovered in the next writing cycle. Hard errors are, instead, a permanent physical failure because of a fault present in the memory device. In practice, hard errors are much less frequent than soft errors.
Error correction code (ECC) is a technique that can be used to reduce the effects of soft errors in memory devices. In some cases, ECC can prove useful for the purpose of recovering some hard errors in the memory device. A well know error correction code is the Hamming code, which appends a series of check bits to a data word as the data word is stored in the memory device. Upon a read operation, the retrieved check bits are compared to recalculated check bits to detect and to locate single bit error. By adding more check bits and appropriately overlapping the subsets of data bits represented by the check bits, these error correcting codes may provide for multiple error corrections and detection. However, ECC requires memory space to store the parity check bits. In particular, the amount of parity check bits can become significant as memory size increases. Most large capacity memory devices often do not have memory space available to store these additional ECC bits. For example, for a memory device with 32 or 36 input-output (I/O), the memory overhead for the ECC bit can exceed 30%.